Universal Remote Control R7 - SPECS SHEET Bedienungsanleitung Seite 23
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Data Sheet ADP5589
Rev. B | Page 23 of 52
DETAILED REGISTER DESCRIPTIONS
Note: N/A throughout this section means not applicable.
Note: All registers default to 0000 0000 unless otherwise specified.
ID Register 0x00
Table 7. ID Bit Descriptions
Bits Name R/W Description
[7: 4] MAN_ID R Manufacturer ID, default = 0001.
[3:0] REV_ID R Rev ID.
Default = 0001 XXXX
INT_STATUS Register 0x01
Table 8. INT_STATUS Bit Descriptions
Bits Name R/W Description
[7: 6] N/A Reserved.
5 LOGIC2_INT R/W 0 = no interrupt.
1 = interrupt due to a general Logic 2 condition.
Write a 1 to this bit to clear it.
4 LOGIC1_INT R/W 0 = no interrupt.
1 = interrupt due to a general Logic 1 condition.
Write a 1 to this bit to clear it.
3 LOCK_INT R/W 0 = no interrupt.
1 = interrupt due to a lock/unlock condition.
The user can read LOCK_STAT (0x02[5]) to determine if LOCK_INT is due to a lock or unlock event.
If LOCK_STAT = 1, LOCK_INT is due to a lock event.
If LOCK_STAT = 0, LOCK_INT is due to an unlock event.
Write a 1 to this bit to clear it.
If lock mode is enabled via the software bit LOCK_EN (0x37[0]), a LOCK_INT is not generated
because the processor knows it just enabled lock mode.
If lock mode is disabled (while locked) via the software bit LOCK_EN, a LOCK_INT is not generated
because the processor knows it just disabled lock mode.
2 OVRFLOW_INT R/W 0 = no interrupt.
1 = interrupt due to an overflow condition.
Write a 1 to this bit to clear it.
1 GPI_INT R/W 0 = no interrupt.
1 = interrupt due to a general GPI condition.
This bit is not set by a GPI that has been configured to update the FIFO and event count.
Write a 1 to this bit to clear it.
This bit cannot be cleared until all GPI_x_INT bits are cleared.
0 EVENT_INT R/W 0 = no interrupt.
1 = interrupt due to key event (press/release), GPI event (GPI programmed for FIFO updates), or
Logic 1/Logic 2 event (programmed for FIFO updates).Write a 1 to this bit to clear it.
Status Register 0x02
Table 9. Status Bit Descriptions
Bits Name R/W Description
7 LOGIC2_STAT R 0 = output from Logic Block 2. (LY2) is low.
1 = output from
Logic Block 2. (LY2) is high.
6 LOGIC1_STAT R 0 = output from Logic Block 1 (LY1) is low.
1 = output from Logic Block 1 (LY1) is high.
5 LOCK_STAT R 0 = unlocked.
1 = locked.
[4:0] EC[4:0] R Event count value. Indicates how many events are currently stored on the FIFO.
- ADP5589 1
- TABLE OF CONTENTS 2
- SPECIFICATIONS 3
- ABSOLUTE MAXIMUM RATINGS 5
- QUICK DEVICE OVERVIEW 7
- 9714-004 7
- DEVICE ENABLE 8
- DEVICE OVERVIEW 8
- EVENT FIFO 9
- KEY SCAN CONTROL 9
- Rev. B 10
- KEY PRESSED 10
- 09714-009 10
- Data Sheet ADP5589 11
- ADP5589 Data Sheet 12
- Key Pad Extension 12
- Ghosting 12
- FIFO Lock/Unlock 12
- GPI Input 15
- REGISTER INTERFACE 19
- REGISTER MAP 21
- ID Register 0x00 23
- INT_STATUS Register 0x01 23
- Status Register 0x02 23
- FIFO_1 Register 0x03 24
- Rev. B 25
- Rev. B 26
- GPI_INT_STAT_A Register 0x13 27
- GPI_INT_STAT_B Register 0x14 27
- GPI_INT_STAT_C Register 0x15 27
- GPI_STATUS_A Register 0x16 28
- GPI_STATUS_B Register 0x17 28
- GPI_STATUS_C Register 0x18 28
- RPULL_CONFIG_A Register 0x19 29
- RPULL_CONFIG_B Register 0x1A 29
- RPULL_CONFIG_C Register 0x1B 30
- RPULL_CONFIG_D Register 0x1C 30
- RPULL_CONFIG_E Register 0x1D 31
- GPI_EVENT_EN_A Register 0x21 32
- GPI_EVENT_EN_B Register 0x22 33
- GPI_EVENT_EN_C Register 0x23 33
- DEBOUNCE_DIS_A Register 0x27 35
- DEBOUNCE_DIS_B Register 0x28 35
- DEBOUNCE_DIS_C Register 0x29 36
- GPO_DATA_OUT_A Register 0x2A 36
- GPO_DATA_OUT_B Register 0x2B 36
- GPO_DATA_OUT_C Register 0x2C 37
- GPO_OUT_MODE_A Register 0x2D 37
- GPO_OUT_MODE_B Register 0x2E 37
- GPO_OUT_MODE_C Register 0x2F 38
- UNLOCK1 Register 0x33 39
- UNLOCK2 Register 0x34 39
- EXT_LOCK_EVENT Register 0x35 39
- UNLOCK_TIMERS Register 0x36 40
- LOCK_CFG Register 0x37 40
- RESET1_EVENT_A Register 0x38 40
- RESET1_EVENT_B Register 0x39 40
- RESET1_EVENT_C Register 0x3A 41
- RESET2_EVENT_A Register 0x3B 41
- RESET2_EVENT_B Register 0x3C 41
- RESET_CFG Register 0x3D 41
- PWM_OFFT_LOW Register 0x3E 42
- PWM_OFFT_HIGH Register 0x3F 42
- PWM_ONT_LOW Register 0x40 42
- PWM_ONT_HIGH Register 0x41 42
- PWM_CFG Register 0x42 42
- CLOCK_DIV_CFG Register 0x43 43
- LOGIC_1_CFG Register 0x44 43
- LOGIC_2_CFG Register 0x45 43
- LOGIC_FF_CFG Register 0x46 44
- POLL_TIME_CFG Register 0x48 44
- PIN_CONFIG_A Register 0x49 45
- PIN_CONFIG_B Register 0x4A 45
- PIN_CONFIG_C Register 0x4B 45
- PIN_CONFIG_D Register 0x4C 46
- GENERAL_CFG_B Register 0x4D 46
- INT_EN Register 0x4E 47
- APPLICATION DIAGRAM 48
- OUTLINE DIMENSIONS 49
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